With the design of heterogeneous systems the designer has to solve a number of challenges. Not only technical challenges but also in the communication area between developers because of the different domain languages used for the integrated systems.
Dyplo provides an operating system extension that addresses these technical challenges and allows designers to talk the same language and use the same interfaces. In this way Dyplo enables you to optimize your system utilization and accelerates your development cycle.
"How to optimize system utilization?"
"What in product solutions do we provide?"
On a CPU, one can make use of an Operating System with a lot of standard functionality, threading and memory management. This enables the possibility to (de)allocate processes at runtime to make a system flexible. On the FPGA, these mechanisms cannot be used. Or can they?
Embedded products are nowadays following the trend with commercial products. Decreasing size, improving performance and increasing battery lifetime. Is it possible to use FPGA’s in such environment?
With a traditional approach you integrate all FPGA functionality in parallel on your FPGA(s) and program the device only once after powering and booting the embedded system. But do you really need all functionality be available in hardware all the time? Do you really want to spend valuable energy on standby functionality, occupy expensive logic resources and have longer development time of your FPGA implementations?
The market requires dedicated solutions to optimize the products for performance and price. This implies modifications in your product line in terms of new hardware and software. How can you keep up with this every increasing development pace?