Dyplo allows you to increase your performance runtime when you need it!

On a CPU, one can make use of an Operating System with a lot of standard functionality, threading and memory management. This enables the possibility to (de)allocate processes at runtime to make a system flexible. On the FPGA, these mechanisms cannot be used. Or can they?

With Dyplo®, you expand the capabilities of an OS onto your FPGA. Enabling runtime (de)allocation of processes on hardware or software. Enabling the application to determine which process runs on which processor, at runtime depending on the performance requirements.

Dyplo® makes use of the partial reconfiguration functionality of modern FPGA’s. By using this partial reconfiguration Dyplo® will re-program a part of the FPGA while the remaining FPGA fabric keeps running without any intervention.

Acceleration of software applications in this way is just a question of launching the accelerator function on an FPGA core and rerouting the data stream within your application. The complexity of partial reconfiguration is solved by Dyplo® and remains completely abstract for the engineers. Dyplo® is currently deployed for Xilinx Zynq® System-on-Chip processor. For the Zynq® it unleashes all the computational power of the FPGA directly to the application software developer, without the need of in-depth FPGA experience. As a side effect, you see multiple smaller FPGA designs instead of a single large design.