Dyplo offers proven FPGA size reduction by using reprogrammable cores on the FPGA!

With a traditional approach you integrate all FPGA functionality in parallel on your FPGA(s) and program the device only once after powering and booting the embedded system. But do you really need all functionality be available in hardware all the time? Do you really want to spend valuable energy on standby functionality, occupy expensive logic resources and have longer development time of your FPGA implementations?

Dyplo® allows you to have multiple functions sharing the same logic resources over time and thus reducing the required size of the FPGA you need for the complete system, cutting cost and power consumption.

When it comes to the size of FPGAs in your design, you are addressing a major cost factor in terms of power consumption, cost of your system and development time. Your applications require always ever more functionality, so bigger FPGAs with higher product cost and longer development times. Dyplo® makes it possible to re-use the same FPGA logic by multiple functions in a similar manner as virtualized memory and multi-threaded applications are used for processors. During program execution you can RUNTIME change the functionality of a reprogrammable core, while the rest of the FPGA keeps running uninterrupted. This dynamic context switching is comparable to software threading. In this context you can also think of real-time execution of functions, requiring true-concurrency. True real-time embedded processing without the burden of proving timing consistency. For this Dyplo® makes use of partial reconfiguration of the FPGA.