Dyplo® enables you to postpone architectural choices to a later stage as you can move functionality across the platform when performance issues arise or are identified.

From a system perspective

Suspend architectural choices to a much later stage as you can move functionality across platform when bottle-necks arise.

From a hardware perspective

Your field of expertise will be valued more, and used more frequently by enabling software engineers to access parts of your domain in a controlled and managed manner. You can focus on your expertise, while full integration of your state of the art work is enabled by the Dyplo® Framework.


From a software perspective

Programming an FPGA is totally different compared to a CPU. Dyplo® extends the FPGA domain to your software domain. The infrastructure is ready to use, and the processor blocks are designed and can be managed in such a way as if you were using software processors, but then much, much more powerful.

Typically, FPGA’s have a fixed behavior once programmed. Dyplo® offers an easy way to reprogram parts of your FPGA resources, on-the-fly!

Out-of-the-box integration of CPU & FPGA

One of the complexities of the Zynq® is the combination of hardware- (FPGA) and software- (CPU) functionality. In order to program your Zynq® product optimally, you need an infrastructure to join the FPGA and CPU. Dyplo® offers this completely.


From an engineering perspective to make your total integrated Zynq® solution work as intended, the key enabler is a good and solid infrastructure. Software and hardware engineers are both experts in their specific domain. Integration is not the main focus of either hardware or software. In order to ensure the best and fastest results, Dyplo® provides a standard out-of-the-box infrastructure to enable the integration. This enables all engineers to focus on what they do best.

AXI compliant

Adding IP blocks to your Dyplo® infrastructure is simple. As long as the code is AXI compliant, hassle free integration is guaranteed.

Data acceleration

The amount of data increases day by day.

The internal structures of the FPGAs are extremely suitable for data processing in terms of available processing power, low energy consumption and memory bandwidth.

Downsides: programming FPGAs is complex, and they have typically fixed functionality.

Dyplo® gives the FPGA this flexibility, totally controlled and managed.

The next step in data acceleration is enabled by Dyplo® giving the FPGA the flexibility to process large data sets with low energy consumption.

Partial Reconfiguration

Partial reconfiguration means that you can re-use, start, stop or copy parts of the cores of your FPGA dynamically when required. For many years, utilization of this specific area of FPGAs has been out of reach for many FPGA users. Dyplo® gives you an easy way to benefit from partial reconfiguration. From a user perspective, simply earmarking blocks for acceleration allows the Dyplo® system to accelerate your application as and when it is required.

Imagine, reducing the size of your fabric with 60% while only using 40% of your fabric simultaneously!

OS Independency

The Zynq® version of Dyplo® is managed by Linux. In future Dyplo® will be ported to many operating systems. On request this process can be advanced, it will only take us a couple of weeks to deliver.