When working with video streams on an FPGA and in need for a way to output the result to a screen, you don’t want to spend valuable time and effort on developing blocks to add this to your design. The Display IP component from Topic Embedded Products is a off-the-shelf block which grants your this capability and is ready to be integrated into your solution.
The display panel interface controller is based on a video frame buffer memory providing software support for bare-metal usage as well as Linux. Using a DMA controlled DDR memory interface, sufficient video bandwidth is available to support HDMI and even 4K video.
The video frame generation is entirely programmable, including V-Sync and H-Sync timing and polarity. Other RGB coded video signals include display enable, backlight intensity control via PWM and the pixel clock. The video output can be a parallel TTL/CMOS output signal or transformed to a standard LVDS panel display output.
DMA based video frame buffer handling
Fully configurable video frame format and signal levels
Optional color space conversion
Parallel pixel interface or LVDS panel display interface